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04/02
Intel Pentium 4 2.4Ghz was released on April 2nd. This CPU is built around the Northwood core and runs on a 400Mhz FSB.
Intel Price cuts occurred on April 14th. See the Intel CPU Prices page for additional information.
AMD Price cuts occurred on April 15th. See the AMD CPU Prices page for additional information.
Trident XP4 Mobile GPU was announced on April 15th. The XP4 contains 30million transistors and is built around a copper interconnect 0.13micron process. The XP4 will be offered at a core clock speed of 250Mhz and a memory clock of 333Mhz DDR (effectively 666Mhz). The memory interface can be either 128-bit (which provides a memory bandwidth of 10.4Gbytes/s) or 64-bit (5.2Gbytes/s).
The architecture of XP4 is fully DirectX 8.1 compliant and features hardware Vertex and Pixel shaders, 4 pixel pipelines with the ability to apply 8 textures per pipeline (which equates to maximum fill rates of 1Gpixel/s and 8Gtextels/s), a multi-view display technology which can output to up to 4 devices simultaneously (from TFT, DVI, CRT and TV out), hardware motion compensation, IDCT decoding and hardware deinterlacing. The XP4 also features CoolPower Technology, which provides dynamic clock gating, frequency scaling and other techniques to help reduce power consumption - the XP4 can run at less than 3W.
XP4 will be offered in a multi-chip module with either 16 or 32Mb of framebuffer. The specifications of XP4 are very impressive, so it will be interesting to see how it performs in real-world applications.
AMD Mobile Athlon XP (Thoroughbred), the successor to Palomino core Athlon 4, was released on April 17th at PR speeds of 1400+ (1.2Ghz), 1500+ (1.3 & 1.33Ghz), 1600+ (1.4Ghz) and 1700+ (1.47Ghz). All CPUs except the 1700+ will be available with a 200 or 266Mhz FSB speed. This marks the introduction of the Thoroughbred core, which is functionally identical to Palomino but is built on a 0.13, rather than 0.18, micron process.
Mobile Pentium 4-M 1.4, 1.5 & 1.8Ghz were released on April 23rd.
Intel Xeon 2.4Ghz, based around the Prestonia core, was released on April 23rd.
nVidia Quadro4 500 Go GL mobile GPU was released on April 23rd.
SiS Xabre 400 GPU was released on April 24th. Xabre 400 is the first of the Xabre GPUs to be released. Xabre is a 0.15micron DirectX 8.1 compliant GPU supporting AGP8X (except SiS 328), FSAA, Dual Display, MPEG decoding assistance and up to 128Mb of DDR memory. There will be four products in the Xabre line:
SiS 328 (Xabre 80) - 183Mhz core, 175Mhz DDR memory, AGP 4X
SiS 332 (Xabre 200) - 250Mhz core, 200Mhz DDR memory (6.4GB/s memory bandwidth)
SiS 334 (Xabre 400) - 250Mhz core, 250Mhz DDR memory (8.0GB/s memory bandwidth)
SiS 336 (Xabre 600) - 275Mhz core, 300Mhz DDR memory (9.6GB/s memory bandwidth)
The Xabre GPUs are expected to compete from the low end to the mid range. The Xabre 200 is targeted to compete with the GeForce4 MX 420 & Radeon 7500 SDR. Likewise the The Xabre 400 targets the GeForce4 MX 440 & Radeon 7500 DDR and the Xabre 600 targets the GeForce4 MX 460 & ATI's forthcoming RV250. Initial benchmarks show the performance of the Xabre GPUs are up to 15% faster than their targeted nVidia GPUs.
05/02
Nintendo Gamecube was released in the UK on May 3rd. See the Japanese Roadmap entry for additional information.
3D Labs P10 VPU was announced on May 3rd. See the release the desktop product's Roadmap entry for additional information.
Intel Pentium 4 (Northwood B) 2.26, 2.4 & 2.53Ghz were released on May 6th. Northwood B is the first Pentium 4 processor to utilise a 533Mhz FSB speed (133Mhz Quad Pumped).
Intel i850E chipset (Tehama-E) for the Pentium 4 was released on May 6th. Tehama-E is essentially identical to the original Tehama chipset (i850), with the only difference being that it is validated for use with 533Mhz FSB processors. Tehama-E officially only supports PC800 RDRAM (and not the newer PC1066 RDRAM) and will make use of Intel's older ICH2 South Bridge.
Matrox Parhelia was announced on May 14th. See the release Roadmap entry for additional information.
Intel Celeron 1.7Ghz (Willamette-128) was released on May 15th. This new Pentium 4 based version of the Celeron is based around the 0.18micron Willamette core, but with the L2 cache reduced to 128Kb. The P4 Celeron utilises Socket 478 & runs on a 400Mhz Quad Pumped bus.
Intel Celeron 1.4Ghz was released on May 15th. This is expected to be the last Celeron based around the Pentium III architecture.
Intel i845E chipset (Brookdale-E) for the Pentium 4 was released on May 20th. Brookdale-E features support for DDR200 and DDR266 but it does not officially supprot DDR333 SDRAM - the forthcoming i845PE and i845GE chipsets will provide this capability. Brookdale-E will support the 533Mhz FSB of the P4 Northwood B and incorporates Intel's ICH4 South Bridge.
Intel i845G chipset (Brookdale-G) for the Pentium 4 was released on May 20th. Brookdale-G is based around Brookdale-E but additionally includes Intel's next generation on-board graphics. The graphics controller is based around a tiling architecture (like that of PowerVR/Kyro) and offers improved 2D output due to a higher frequency (350Mhz) integrated RAMDAC, as well as improved 3D performance compared to the i752 chip found in the i810/i815 series. The 3D core features a 200Mhz clock speed with 1 pixel pipeline and 2 texture units (which also offers 4 textures per rendering pass). The core does not contain an on-board T&L unit. The maximum fill rates of the 3D core are 200Mpixels/s and 400Mtexels/s, with real-world throughput being quite similar due to its tiling architecture. Initial benchmarks have shown that the 3D performance is around that of a GeForce2 MX 200 - adequate for on-board graphics, but quite poor compared with modern 3D boards. Brookdale-G also features support for an external AGP 4X graphics port.
Intel i845GL chipset (Brookdale-GL) for the Pentium 4 was released on May 20th. Brookdale-GL is the 'Lite' version of Brookdale-G, lacking support for the 533Mhz FSB speed of Northwood B (i.e. targeted at the Pentium 4 Celeron) and featuring support for only 2 DIMMs. Brookdale-GL will feature the same integrated graphics as Brookdale-G, but it will not support external AGP cards.
Intel ICH4 south bridge was released on May 20th, alongside the i845x chipsets. ICH4 is the successor to the ICH3 south bridge which was introduced with Intel's mobile i830M chipset. ICH4 will feature support for 6 USB 2.0 ports in addition to the featureset of ICH3.
VIA P4X266E chipset for the Pentium 4 processor was released on May 22nd. The P4X266E is based around the P4X266A, but additionally includes support for a 533Mhz FSB speed and compatibility with VIA's new VT8235 South Bridge. VIA's VT8235 was first introduced with the P4X333 chipset and includes integrated USB2.0 support.
Netscape 7.0 PR1 was released on May 23rd. New features include email spell checking, Internet Radio, Tabbed browsing, the ability to save whole web pages, Print Preview and more.
Intel Price cuts for the Pentium 4 series occurred on May 26th. See the Intel CPU Prices page for additional information.
AMD Price cuts for occurred on May 29th. See the AMD CPU Prices page for additional information.
Intel Itanium 2 (McKinley), the IA64-based successor to Merced (Itanium), was announced on May 30th. The first Itanium 2 processors are expected to become available in Mid 2002 at clock speeds of 1Ghz (3Mb cache) and 900Mhz (1.5Mb cache). McKinley is built on a 0.18micron process and has a huge die size - 465mm squared and containing 220m transistors (compared to Merced's 25m) in its 3Mb L3 cache form. Unlike Itanium, which uses a 64-bit double-pumped 133Mhz system bus, McKinley will run on a 128-bit double-pumped 200Mhz bus, giving a memory bandwidth of 6.4Gb/s compared to Itanium's 2.1Gb/s. The cache subsystem has been improved quite substantially, with all three levels on cache now being integrated onto the CPU die. The L1 cache consists of 16Kb Data and 16Kb Instruction, with a latency of 1 cycle, compared to 2 in Itanium. The 256Kb L2 cache now has a 5 cycle latency (compared with 12 on Itanium) and the L3 cache is on-die, also with a 5 cycle latency (compared to the 21 cycle delay in the off-die L3 cache of Itanium). McKinley features an 8 stage execution pipeline (compared to Merced's 10 stage pipeline), up to 6Mb of L3 cache (1.5Mb and 3Mb initially) and 6 integer units (4 M-Units and 2 I-Units) compared to the 4 of Itanium (2 M-Units and 2 I-Units). McKinley is also expected to feature less restrictive issue rules (the way instructions can be bundled and issued to the CPU - Itanium can concurrently execute 2 EPIC bundles of 3 instructions each, but the rules of this bundling may be relaxed in McKinley) and reduced instruction latencies. The processor itself will be housed in a cartridge containing an integrated PSU. The performance of a 1Ghz part is expected to be around 1.7 times that of an 800Mhz Itanium (initial benchmarks suggest 1.5 to 2% depending on the application), making McKinley approximately 35% faster per clock cycle.
Intel E8870, formally known as the i870, chipset for Itanium 2 (McKinley) was announced on on May 30th with availability expected in Mid 2002. The E8870 is expected to support up to 4 CPU's per chipset and 8Gb of DDR SDRAM per processor. The chipset consists of three parts - a node controller (equivalent to a Northbridge), an I/O hub (equivalent to a Southbridge) and a Switch chip for scalability. The switch chip consists of a Scalability Port Switch and a Scalable Node Controller. The Scalable Port Switch (SPS) connects up four processors together, via 6.4GB/s point-to-point interconnects, and connects to the I/O hub. The SPS also allows chips to snoop each others local memory. The Scalable Node Controller (SNC) links each processor to dual channel DDR main memory (up to 8GB - 2 banks of 4x1GB DIMMs) and links the 4-unit processor clusters together. The I/O hub supports PCI-X and legacy protocols, and links the processor clusters to these I/O devices. The E8870 is expected to support up to 512-way SMP.
DirectX 9 Beta 1 was released to Beta testers on the May 31st. See the final release Roadmap entry for additional information.
06/02
VIA C3 1Ghz was released on June 3rd.
S3 Savage XP, formally Zoetrope, was announced on June 3rd, with availability expected within the month. Savage XP is built on a 0.15micron process and features 2 pipelines with 2 texture units per pipeline, DirectX 7 hardware T&L, Duo-View Plus dual screen technology, a 350Mhz RAMDAC, DVA and TV Out. Savage XP is expected to be introduced with a memory clock of 175Mhz DDR, over a 128-bit bus, providing 5.7GB/s of memory bandwidth and will run at core clock speeds up to 166Mhz. Performance is expected to be around that of a GeForce4 MX 420.
Windows XP SP1 Beta was released to Beta testers on June 5th. See the release Roadmap entry for additional information.
Mozilla 1.0 was released on June 6th. Mozilla is the Open Source version of Netscape containing a web browser, email reader and chat client. Mozilla 1.0 offers excellent support for CSS2, DOM2, and XHTML. Additionally Mozilla 1.0 supports JavaScript 1.5, SOAP 1.1, XSLT, XPath 1.0, MathML and FIXptr for XML data exchange and manipulation.
Rambus PC1066 (Hastings) memory technology became available during Q2. Hastings offers a 33% performance increase over standard RDRAM by increasing the data rate from 800Mhz to 1066Mhz, offering a peak memory bandwidth of 2.1GB/s.
Rambus RIMM4200 memory was launched on June 6th. RIMM4200 is a 32-bit wide, 232-pin version of the standard 16-bit, 184-pin PC1066 RIMM, offering a peak memory bandwidth of 4.2GB/s. Perhaps its main advantage in the PC market will be its equivalence to 2 channels of PC1066. This means that motherboards can offer a single 32-bit RIMM in preference to two 16-bit RIMMs, and memory upgrades can be carried out through the purchase of a single RIMM (currently RIMMs must be purchased in sets of two).
AMD Athlon XP (Thoroughbred), the 0.13 micron successor to Palomino core Athlon XP, was released on June 10th at clock speeds between 1700+ (1.47Ghz) and 2200+ (1.8Ghz). Thoroughbred has the same featureset as Palomino, but contains minor changes to the core to reduce the transistor count from 37.5 to 37.2 million (mostly through re-positioning the L2 cache). Thoroughbred measures 80mm2 as opposed to the 128mm2 of Palomino.
Intel Celeron 1.8Ghz was released on June 12th.
Matrox Parhelia 512 GPU series was announced on June 18th with first shipments expected to start on June 30th. The 0.15micron Parhelia core contains 80 million transistors and will initially be launched at a core clock speed of 220Mhz (Retail) and 200Mhz (OEM), with memory clocks of 275Mhz DDR (Retail) and 250Mhz DDR (OEM). Parhelia can address up to 256Mb of local memory and is AGP 4X compatible (initial reports specified AGP 8X). Initial cards will contain 128Mb while future versions will be outfitted with 64 and 256Mb.
The basic architecture of Parhelia consists of 4 pixel pipelines with 4 Texture Units per pipeline (compared to 2 texture units/pipeline in GF4) and 4 Vertex Shaders (compared to 2 Vertex Shaders in the GF4). This core will access memory over a 256-bit memory bus (compared with the 128-bit bus used by the GF4 and Radeon 8500), offering up to 17.6GB/s of memory bandwidth (Retail version - the OEM version has a memory bandwidth of 16GB/s). The Graphics pipeline is different to GF4/Radeon 8500 in that the Vertex Shaders are DirectX 9 compliant - i.e. they correspond to the Vertex Shader 2.0 specification. The Pixel Shaders are still only DirectX 8.1 compatible, but they are 5 stage (rather than 2 stage in the GF4), meaning that 5 pixel operations can be executed in a single pass, avoiding costly multipassing.
As well as incorporating Vertex Shader 2.0 technology, Parhelia's contains a DirectX 9 compatible Hardware Displacement Mapping engine. The HDM engine consists of a Depth Adaptive tessellation unit and a Vertex Texturing unit. The Vertex Texturing Unit handles displacement mapping, which basically tessellates a surface given a 2D texture, whose pixels correspond to the height of the point on a plane. The Depth Adaptive Tessellation Unit tries to reduce the number of unnecessary vertices in a scene by dynamically reducing the polygon count of distant objects.
The Parhelia core also introduces a new and sophisticated form of Anti Aliasing, which Matrox call Fragment Anti Aliasing (FAA). Rather than applying Anti Aliasing to all pixels, which is what occurs in current FSAA schemes, FAA performs Anti Aliasing only on pixels surrounding edges. The FAA engine takes up quite a large transistor count, but allows high quality Anti Aliasing to be performed with a minimal performance hit. Unlike FSAA algorithms, the performance hit of FAA does not increase significantly when running at higher resolutions.
It should be noted that Parhelia only offers very limited occlusion logic to reduce memory bandwidth requirements - Fast Z-Clear is present, but complex logic such as ATI's HyperZ and nVidia's Visibility subsystem were not included to reduce the die size. As Parhelia has a significant memory bandwidth advantage over the R200 and NV25 this should not have a great performance hit with many of today's games.
The 2D featureset of Parhelia is also very impressive. Parhelia contains 2x400Mhz RAMDACs (2048x1536x32@80Hz), 2xTDMS interfaces (1920x1200x32) and a TV-Out all with 10-bit/channel colour support. Parhelia also supports hardware accelerated text Anti Aliasing for Windows XP's ClearType technology. As always with Matrox products, the 2D image quality is excellent - Matrox's 'UltraSharp' RAMDACs and high quality 5th order output filters give a significantly better frequency response than those from ATI and nVidia (which generally use inferior 3rd order filters). The two built in RAMDACs allow for the full range of DualHead facilities present in the G400/500 range, but Parhelia also allows for a third external 230Mhz RAMDAC to be used to give Triple Head functionality (the resolution is limited to 1600x1200, with a maximum resolution of 3840x1024 across all three displays in 32-bit - i.e. 1280x1024 per head). As well as allowing three monitors to be used for standard Desktop applications Matrox are promoting the idea of 'Surround Gaming'. This allows three monitors to be used inside games, with the left and right monitors providing peripheral vision for the centre monitor.
Initial benchmarks show that the 3D performance of Parhelia is relatively poor compared to the GeForce4 Ti and even the Radeon 8500, despite its impressive specification. Excluding benchmark results that utilise Matrox's Fragment Anti Aliasing, Parhelia's 3D performance is worse than even the low-end GeForce4 Ti 4200 in virtually all benchmarks, and is almost always is outperformed by the Radeon 8500. When utilising the highly efficient FAA algorithm, however, the performance is more respectable, but still can't really compete with the high-end GeForce4 Ti 4600. With future driver revisions and games that utilise high levels of Quad texturing and DX8 Vertex and Pixel shader programs Parhelia may become more competitive. Parhelia is a good solution for those who wish to use Surround Gaming, always play with Anti-Aliasing turned on or want the option of having three displays with excellent 2D quality, but a standard 3D gamer would be better served by an ATI or nVidia card.
The Retail Parhelia is expected to cost around $399 (220Mhz core, 275Mhz, 128Mb DDR), while the OEM version is expected at around $350 (200Mhz core, 250Mhz, 128Mb DDR).
AMD Athlon MP 2100+, the last 0.18 micron Palomino core Athlon MP, was released on June 19th.
nVidia GeForce4 Go series of mobile GPUs was released on June 21st. The details of the GeForce4 Go core can be found on he announcement Roadmap entry. There are three products in the GeForce4 Go line, two of which are available in discrete (GPU only) or MAP (On-board memory) packaging.
GeForce4 Go 440 (Discrete) - 220Mhz core, 220Mhz DDR (128-bit
bus)
GeForce4 Go 440 (MAP) - 190Mhz core, 64Mb 200Mhz DDR (128-bit bus)
GeForce4 Go 420 (Discrete) - 200Mhz core, 200Mhz DDR (64-bit bus)
GeForce4 Go 420 (MAP) - 190Mhz core, 32Mb 200Mhz DDR (64-bit bus)
GeForce4 Go 410 (MAP) - 190Mhz core, 16Mb 200Mhz SDR (64-bit bus)
The GeForce4 Go 440 performs very similarly to the GeForce4 MX 440, with the discrete solutions performing slightly faster than those using the MAP format due to the clock speed differences.
Mobile Pentium 4-M 1.9 & 2.0Ghz were released on June 24th.
Mobile Celeron-M 1.4 & 1.5Ghz were released on June 24th. These processors are based around the 0.13 micron Pentium 4 based Northwood core and feature a 400Mhz FSB and 256Kb L2 cache.
Mobile Celeron-M 1.33Ghz was released on June 24th. This processor is based around the 0.13 micron, Pentium III based Tualatin core and features a 133Mhz FSB.
Intel Itanium 1Ghz is expected to be released in June (possibly cancelled).
Windows.NET Server RC1 is expected to be released towards the End of June. See the release Roadmap entry for additional information.
Q2 02
Intel Xeon (Prestonia) 2.4Ghz is expected to be released in Q2.
Intel Madison IA64 CPU is expected to be piloted in Q2. Madison is the 0.13 micron successor to the McKinley ('Itanium 2') IA64 CPU. Madison is expected to based around the McKinley core, but will contain a larger 6Mb L3 cache.
VIA Mobile C5N (Ezra T core) CPU is expected to be released in Q2, at clock speeds between 900Mhz and 1.2Ghz. The C5N core is based around the C5M core, but is built on a superior copper interconnect process.
VIA KM333 chipset for the AMD Athlon processor is expected to be released in Q2. The KM333 is the AMD version of the P4M333 Intel chipset, featuring integrated Zoetrope graphics.
SiS 746 chipset, for the AMD Athlon processor series, is expected to be released in towards the end of Q2. SiS 746 is the successor to the SiS 745, adding support for DDR400 SDRAM. The SiS 746 will feature a 1066MB/s link to the SiS 963 South Bridge which offers support for ATA133, 3 x IEE1394 and 6 x USB2.0 ports.
ALi M1672 chipset for the Intel P4 platform is expected to be released in Q2. The M1672 adds Triden XP integrated graphics to the M1671 chipset core, but does not support DDR333 or a 533Mhz FSB speed.
ALi ALADDiN P4A (M1671A) chipset for the Intel P4 platform is expected to be released in Q2. The M1671A is the successor to the M1671, adding support for the 533Mhz FSB speed of Northwood B and DDR333 SDRAM.
Motorola PowerPC G5 processor is expected to be released in Q2 at initial clock speeds of 800Mhz to 1.6Ghz on a 0.13micron SOI process. The G5 core is expected to feature a 10 stage pipeline (compared to 7 in the G4), which allows a higher clock speed than the G4 core but reduces the IPC (instructions per clock) - this is a similar tactic to that used by Intel with the Pentium 4. The Front Side Bus speed of this processor is expected to be 400Mhz, which may be implemented by quad pumping the bus like the Pentium 4.
VIA P4M333 chipset for the Pentium 4 processor is expected to be released in Q2. The P4M333 will be based around the P4X333, but will include an integrated S3 Zoetrope graphics core. Zoetrope is expected to feature 2 rendering pipelines with 2 texture units per pipeline.
